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F75111RG датащи(PDF) 23 Page - Feature Integration Technology Inc.

номер детали F75111RG
подробное описание детали  Low Power GPIO Datasheet
PDF  45 Pages
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производитель  FINTEK [Feature Integration Technology Inc.]
домашняя страница  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F75111RG датащи(HTML) 23 Page - Feature Integration Technology Inc.

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July, 2007
V0.27P
- 21 -
F75111
3
STS_GP13ED
GE
RW
VSB3V
Indicate GPIO13 Edge Status. If set to 1, the edge of GPIO13 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
2
STS_GP12ED
GE
RW
VSB3V
Indicate GPIO12 Edge Status. If set to 1, the edge of GPIO12 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid. If this bit
serves as IRQ/SMI#, this bit has no effect.
1
STS_GP11ED
GE
RW
VSB3V
Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO11 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
0
STS_GP10ED
GE
RW
VSB3V
Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO10 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
7.20 GP1X IRQ or SMI# Enable Register – Index 0x1A
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP17IRQ
R/W
VSB3V
Enable GPIO17 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO17 to generate IRQ or SMI#.
6
EN_GP16IRQ
R/W
VSB3V
Enable GPIO16 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO16 to generate IRQ or SMI#.
5
EN_GP15IRQ
R/W
VSB3V
Enable GPIO15 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO15 to generate IRQ or SMI#.
4
EN_GP14IRQ
R/W
VSB3V
Enable GPIO14 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO14 to generate IRQ or SMI#.
3
EN_GP13IRQ
R/W
VSB3V
Enable GPIO13 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO13 to generate IRQ or SMI#.
2
EN_GP12IRQ
R/W
VSB3V
Enable GPIO12 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO12 to generate IRQ or SMI#.
1
EN_GP11IRQ
R/W
VSB3V
Enable GPIO11 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO11 to generate IRQ or SMI#.
0
EN_GP10IRQ
R/W
VSB3V
Enable GPIO10 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO10 to generate IRQ or SMI#.
7.21 GP1X Output Driving Enable – Index 0x1B
Power-on default [7:0] =0000_1000b
Bit
Name
R/W
PWR
Description
7
EN_GP17_OBUF
R/W
VSB3V
Enable GPIO17 drive high buffer. If this bit is set to 0, the pin GPIO17
will be I/OD pin, if set to 1 the pin GPIO17 is I/O pin.
6
EN_GP16_OBUF
R/W
VSB3V
Enable GPIO16 drive high buffer. If this bit is set to 0, the pin GPIO16
will be I/OD pin, if set to 1 the pin GPIO16 is I/O pin.



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