F75111RG datasheet(19/45 Pages) FINTEK

19 / 45 page

July, 2007

V0.27P

- 17 -

F75111

GP16_PSTS

VSB3V

Read the GPIO16 data on the pin.

GP15_PSTS

VSB3V

Read the GPIO15 data on the pin.

GP14_PSTS

VSB3V

Read the GPIO14 data on the pin.

GP13_PSTS

VSB3V

Read the GPIO13 data on the pin.

GP12_PSTS

VSB3V

Read the GPIO12 data on the pin.

GP11_PSTS

VSB3V

Read the GPIO11 data on the pin.

GP10_PSTS

VSB3V

Read the GPIO10 data on the pin.

7.13 GPIO1x Level/Pulse Control Register – Index 13h

Power-on default [7:0] =0000_0000b

Bit

Name

R/W

PWR

Description

GP17_OMODE

R/W

VSB3V

GPIO 17 output mode. 0 – level, 1 – pulse.

GP16_OMODE

R/W

VSB3V

GPIO 16 output mode. 0 – level, 1 – pulse.

GP15_OMODE

R/W

VSB3V

GPIO 15 output mode. 0 – level, 1 – pulse.

GP14_OMODE

R/W

VSB3V

GPIO 14 output mode. 0 – level, 1 – pulse.

GP13_OMODE

R/W

VSB3V

GPIO 13 output mode. 0 – level, 1 – pulse.

GP12_OMODE

R/W

VSB3V

GPIO 12 output mode. 0 – level, 1 – pulse. If this serves as IRQ/SMI#

mode, it will have same function.

GP11_OMODE

R/W

VSB3V

GPIO 11 output mode. 0 – level, 1 – pulse.

GP10_OMODE

R/W

VSB3V

GPIO 10 output mode. 0 – level, 1 – pulse.

7.14 GPIO1x Pulse Width Control Register – Index 14h

Power-on default [7:0] =0000_0000b

Bit

Name

R/W

PWR

Description

7:2

Reserved

R/W

VSB3V

Reserved. Read return 0.

1:0

GP1_PSWDTH[1:0

]

R/W

VSB3V

GPIO1x pulse width. If set the GPIO1x to pulse mode, the pulse

width can be defined as follows.

00b – 500us (Default)

01b – 1ms

10b – 20ms

11b – 100ms

F75111RG датащи(PDF) 19 Page - Feature Integration Technology Inc.

F75111RG датащи(HTML) 19 Page - Feature Integration Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

датащи скачать

ссылки URL