THS8136IPHPR datasheet(11/17 Pages) TI

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ANALOG (DAC) OUTPUTS ELECTRICAL CHARACTERISTICS

THS8136

www.ti.com ........................................................................................................................................................................................... SLES236 – NOVEMBER 2008

over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),

37.5-

Ω load termination (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC resolution

Bits

Static, best fit, RGB with sync insertion (700 +

-1/1 –2.5/1.5

sync)

INL

Integral nonlinearity

LSB

Static, best fit, generic mode, 1.2 V output range

–1/1

Static, RGB with sync insertion (700 + sync)

–0.4/0.4

±1

DNL

Differential nonlinearity

LSB

Static, generic mode, 1.2 V output range

-0.4/0.4

Power supply ripple rejection ratio of

PSRR

f = DC(1)

38.5

DAC output (full scale)

Vrefo

Voltage reference output

1.12

1.16

1.20

VREF output resistance

284

Ω

KIMBAL

Imbalance between DACs(2)

CLK = 80 MSPS, video mode

–2

1.8

VOC

DAC output compliance voltage

0.7

1.2

Generic DAC mode

CLK = 80 MSPS(3)

18.67

19.5

IFS

RGB with sync insertion enabled

CLK = 80 MSPS(3)

29.3

tRDAC

DAC output current rise time

CLK = 80 MSPS, 10 to 90% of full scale(4)

2.8

3.3

3.6

tFDAC

DAC output current fall time

CLK = 80 MSPS, 10 to 90% of full scale(4)

2.8

3.3

3.6

Measured from CLK = VIH(min) to 50% of

td(A)

Analog output delay

4.5

full-scale transition(5)

Measured from 50% of full scale transition on

Analog output settling time

output to output settling, within 2%(4)

(1)

PSRR is measured with a 0.1-

µF capacitor between the COMP and AV

DD pins and with a 0.1-µF capacitor connected between the VREF

and AVSS pins. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a

double-terminated 75

Ω (= 37.5 Ω) load. PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits

are from characterization only.

(2)

The imbalance between DACs applies to all possible pairs of the three DACs.

(3)

Values at RFS = RFS(nom)

(4)

From characterization only. Measured on the AG channel with RFS = RFS(nom).

(5)

This value excludes the digital process delay, tD(D). Limit are from characterization only.

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