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THS8136IPHPR датащи(PDF) 9 Page - Texas Instruments

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номер детали THS8136IPHPR
подробное описание детали  TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC
PDF  17 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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THS8136IPHPR датащи(HTML) 9 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
(1)
POWER DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
THS8136
www.ti.com ........................................................................................................................................................................................... SLES236 – NOVEMBER 2008
over operating free-air temperature range (unless otherwise noted)
AVDD to AVSS
–0.5 V to 3.6 V
Supply voltage
DVDD to DVSS
–0.5 V to 1.95 V
AVSS to DVSS
–0.5 to 0.5 V
Digital input voltage range to DVSS
–0.5 V to (DVDD + 0.5) V
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–55°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TA ≤ 25°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
POWER RATING
POWER RATING
Low-K(2)
TQFP-48-PHP
33.0°C/W
67.60°C/W
1.18 W
0.296 W
High-K(3)
TQFP-48-PHP
33.0°C/W
29.04°C/W
2.75 W
0.689 W
(1)
Specified with 105°C maximum junction temperature (TJ).
(2)
Specified with thermal pad not soldered to the PCB
(3)
Specified with thermal pad soldered to 2-oz Cu plate PCB thermal plane.
MIN
NOM
MAX
UNIT
Power Supply
AVDD
3
3.3
3.6
V
DVDD
1.65
1.8
1.95
V
Digital and Reference Inputs
VIH
High-level input voltage
1.2
DVDD
V
VIL
Low-level input voltage
DVSS
0.7
V
fCLK
Clock frequency
0
180
MHz
CLK
tw(CLKH)
Pulse duration, clock high
40%
60%
period
CLK
tw(CLKL)
Pulse duration, clock low
40%
60%
period
RFS(nom)
FSADJ resistor(1)
3.8
k
(1)
RFS should be chosen such that the maximum full-scale DAC output current (IFS) does not exceed the maximum stated level. This yields
the nominal output voltage compliance at the nominal load termination of 37.5
Ω.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): THS8136



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