THS8136IPHPR datasheet(10/17 Pages) TI

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POWER SUPPLY ELECTRICAL CHARACTERISTICS

DIGITAL INPUTS – DC ELECTRICAL CHARACTERISTICS

THS8136

SLES236 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com

over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),

37.5-

Ω load termination (unless otherwise noted)

PARAMETER

TEST CONDITIONS(1)

MIN

TYP(2)

MAX(3)

UNIT

CLK = 80 MSPS

Generic (700 mV)

CLK = 180 MSPS

CLK = 80 MSPS

110

112

Operating supply current,

IAVDD

Generic (1.2 mV)

analog

CLK = 180 MSPS

110

112

CLK = 80 MSPS

102

Sync Insertion (700 mV + Sync)

CLK = 180 MSPS

103

CLK = 80 MSPS

Generic (700 mV)

CLK = 180 MSPS

CLK = 80 MSPS

Operating supply current,

IDVDD

Generic (1.2 mV)

digital

CLK = 180 MSPS

CLK = 80 MSPS

Sync Insertion (700 mV + Sync)

CLK = 180 MSPS

CLK = 80 MSPS

238

290

Generic (700 mV)

CLK = 180 MSPS

270

329

CLK = 80 MSPS

388

434

Power dissipation

Generic (1.2 mV)

CLK = 180 MSPS

419

475

CLK = 80 MSPS

334

398

Sync Insertion (700 mV + Sync)

CLK = 180 MSPS

366

441

(1)

A multiburst RGB input test pattern was used in all cases.

(2)

TYP current and PD measured at AVDD = 3.3 V and DVDD = 1.8 V.

(3)

MAX current and PD measured at AVDD = 3.6 V and DVDD = 1.95 V.

over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),

37.5-

Ω load termination (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current

AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 1.95 V

µA

IIL

Low-level input current

AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 0 V

–1

µA

IIH(CLK)

High-level input current, CLK

AVDD = 3.3 V, DVDD = 1.8 V, CLK at 1.95 V

–1

µA

IIL(CLK)

Low-level input current, CLK

AVDD = 3.3 V, DVDD = 1.8 V, CLK at 0 V

–1

µA

Input capacitance

TA = 25°C

Setup time, data and control inputs

1.5

Hold time, data and control inputs

500

Digital process delay time from first

CLK

td(D)

registered color component of

7.5

periods

pixel(1)

(1)

This parameter is specified by design. The digital process delay is defined as the number of CLK cycles required for the first registered

color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the

DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.

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