26

6399A–DRMSD–13-Oct-08

ATSAM2553

Key velocity & Status:

• SRQ: If 1, indicates that the velocity detection is completed and that this key requests

attention from the P16. In this case BUSY = 0, ON and VEL hold valid information.

• ON: 1 indicates key-on, 0 indicates key-off. Valid only if SRQ = 1.

• BUSY: Used internally by the scanning hardware, indicates “velocity detection in progress”.

• VEL: From 0 to 255, valid only if SRQ = 1, indicates the time between contacts. Time is

depending on Scanning divider and Scanning matrix configuration.

– 0 < VEL < 128: TimeCount = VEL x 41.6 µs.

– 128 < VEL < 192: TimeCount = 128 x 41.6 µs + (VEL - 128) x 2 x 41.6µs.

– 192 < VEL < 224: TimeCount = 2 x 128 x 41.6 µs + (VEL - 192) x 4 x 41.6µs.

– 224 < VEL < 240: TimeCount = 3 x 128 x 41.6 µs + (VEL - 224) x 8 x 41.6µs.

– 240 < VEL < 255: TimeCount = 4 x 128 x 41.6 µs + (VEL - 240) x 16 x 41.6µs.

• LED data: The P16 should write to these locations the MK information which should appear

to the MK[10:0] pins at row[2:0] time.

• Switch data: These locations hold the BR information read from the BR[10:0] pins at row[3:0]

time.

• ADC data: These locations represent the analog voltage at VIN pin at row[3:0] time, from 0

(VIN = AGND) to 03FFH (VIN = VA33). ADC data are sampled with 10-bit precision and the

result is stored on 8 bits.

12.6

GPIO

P[3:1] are controlled by the ATSAM97xx config and control/status registers (refer to

prgdvkit.pdf).

P0 in normal mode is controlled by the ATSAM97xx config and control/status registers (refer to

prgdvkit.pdf).

The ATSAM2553 additional GPIO control/status register controls P0 normal and alternate

mode.

The GPIO register is located at address 0xF in the I/O mapping.

Data bit number

Write

Read

7x

x

6x

x

5x

x

4

P0 Alt

P0 Alt

3

x

DBCLK

2

DBDATA OUT

DBDATA IN

1

DBACK

DBACK status

0

DBDATA Output Enable

DBCLK