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www.semtech.com

POWER MANAGEMENT

SC1211

Applications Information (Cont.)

tor. The capacitor value can be calculated based on the

voltage ripple on the capacitor,

Typically, it is recommended to use a 1uF ceramic ca-

pacitor with 25V rating and a commonly available diode

IN4148 for the bootstrap circuit. In addition, a small re-

sistor (one ohm) has to be added in between DRN of the

SC1211 and the Phase Node. The resistor is used to

allievate the stress of the SC1211 from exposing to the

negative spike at the Phase node. A negative spike could

occur at the Phase Node during the top FET turn-off due

to parasitic inductance in the switching loop. The spike

could be minimized with a careful PCB layout. In those

applications with TO-220 package FETs, it is recom-

mended to use a clamping diode on the DRN pin to miti-

gate the impact of the excessive phase node negative

spike.

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

Filters for Supply Power

For VREG pin of the SC1211, it is recommended to use

a 1uF to 4.7uF, 25V rating ceramic capacitor for

decoupling.

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LAYYYYYOUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

The switching regulator is a high di/dt power circuit. Its

Printed Circuit Board (PCB) layout is critical. A good lay-

out can achieve an optimum circuit performance while

minimized the component stress, resulting in better sys-

tem reliability. For a multi-phase voltage regulator, the

SC1211 driver, FETs, inductor, and supply decoupling

capacitors in each phase have to be considered as a

whole during PCB layout. Refer to Semtech SC2643VX/

SC1211 EVB Layout Guideline.

For the SC1211 driver, the following guidelines are typi-

cally recommended during PCB layout:

1. Place the SC1211 close to the FETs for shortest gate

drive traces and ground return paths.

2. Connect bypass capacitors as close as possible to

decoupling pins (VREG and VIN) and PGND. The trace

length of the decoupling capacitor on VREG pin should

be no more than 0.2” (5mm).

3. Locate the components of the bootstrap circuit close

to the SC1211.

SOLDERING CONSIDERA

SOLDERING CONSIDERA

SOLDERING CONSIDERA

SOLDERING CONSIDERA

SOLDERING CONSIDERATION

TION

TION

TION

TION

The exposed die pad of the SC1211 is used for ground

Solder Pad

Solder Mask

Vias

Copper

return and thermal release of the driver. The pad must

be soldered to the ground plane that is further connected

to the system ground in the inner layer through multiple

vias. For better electrical and thermal performance, it is

recommended to use all copper available under the driver

as the ground plane, and place the vias as close as pos-

sible to the solder pad. Meanwhile, the vias have to be

masked out to prevent solder leakage during reflow. The

layout arrangement is detailed in the above figure, which

also can be found in the “Land Pattern – Power SOIC-8”

section.