LPC2921 datasheet(51/81 Pages) PHILIPS

51 / 81 page

LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

51 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

6.16 Vectored interrupt controller

The LPC2921/2923/2925 contains a very flexible and powerful Vectored Interrupt

Controller (VIC) to interrupt the ARM processor on request.

The key features are:

• Level-active interrupt request with programmable polarity.

• 56 interrupt-request inputs.

• Software-interrupt request capability associated with each request input.

• Interrupt request state can be observed before masking.

• Software-programmable priority assignments to interrupt requests up to 15 levels.

• Software-programmable routing of interrupt requests towards the ARM-processor

inputs IRQ and FIQ.

• Fast identification of interrupt requests through vector.

• Support for nesting of interrupt service routines.

6.16.1 Functional description

The Vectored Interrupt Controller routes incoming interrupt requests to the ARM

processor. The interrupt target is configured for each interrupt request input of the VIC.

The targets are defined as follows:

• Target 0 is ARM processor FIQ (fast interrupt service)

• Target 1 is ARM processor IRQ (standard interrupt service)

Interrupt-request masking is performed individually per interrupt target by comparing the

priority level assigned to a specific interrupt request with a target-specific priority

threshold. The priority levels are defined as follows:

• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never

lead to an interrupt)

CLK_TMR0

BASE_TMR_CLK

CLK_TMR1

BASE_TMR_CLK

CLK_TMR2

BASE_TMR_CLK

CLK_TMR3

BASE_TMR_CLK

CLK_ADC1

BASE_ADC_CLK

CLK_ADC2

BASE_ADC_CLK

CLK_TESTSHELL_IP

BASE_CLK_TESTSHELL

CLK_USB

BASE_USB_CLK

Table 29.

Branch clock overview …continued

Legend:

‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored

‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored

‘+’ Indicates that the related register bit is readable and writable

Branch clock name

Base clock

Implemented switch on/off

mechanism

WAKE-UP

AUTO

RUN

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