| поискавой системы для электроныых деталей |
|
SC471AEVB датащи(PDF) 16 Page - Semtech Corporation |
|
|
|||||||||||||||||||||||||||||
SC471AEVB датащи(HTML) 16 Page - Semtech Corporation |
|
16 / 27 page ![]() 16 © 2008 Semtech Corp. SC471/SC471A www.semtech.com POWER MANAGEMENT When G0 or G1 changes state, PGD is immediately latched into its present state for 32 clock cycles while VOUT and FB change to the new level, after which the latch is disabled. Output Over-Voltage Protection In steady state operation, when FB exceeds 20% of nominal (900mV), DL latches high and the low-side MOSFET is turned on. DL stays high and the SMPS stays off until the EN/PSV input is toggled or VCC is recycled. There is a 5μs delay built into the OVP detector to prevent false transitions. PGD is also held low after an OVP. During G0/G1 transitions, the OVP threshold is temporarily increased to 50% above nominal (1.125V), for 32 clock cycles. This is for cases where the output voltage is slewing from a higher to a lower voltage: the change in G0/G1 affects the D0/D1 pins immediately, which in turn affects the FB voltage immediately. The increase in OVP from 20% to 50% is to prevent nuisance OVP tripping caused by the immediate change at FB. It also protects against the case of output overshoot for a lower to higher VOUT transition. Note: since the temporary OVP point is 50%, it is not possible to change the output voltage down by more than 50% in one step. To transition the output voltage more than 50% requires at least two sequential step transitions to prevent OVP, or the use of the RC smoothing circuit. Output Under-Voltage Protection When FB falls 30% below nominal (525mV) for eight consecutive clock cycles, the output is shut off; the DL/ DH drives are pulled low to tristate the MOSFETS, and the SMPS stays off until the Enable input is toggled or VCC is recycled. POR and UVLO Under-voltage lockout circuitry (UVLO) inhibits switching and tristates the DH/DL drivers until VCC rises above 4.4V. An internal power-on reset (POR) occurs when VCC exceeds 4.4V, which resets the fault latch and the soft- start counter, to prepare the PWM for switching. At this time the SC471/A will come out of UVLO and begin the soft-start cycle. Soft-Start The soft-start is accomplished by ramping the FB comparator’s internal reference from zero to 0.75V in 30mV increments. Each 30mV step typically lasts for eight clock cycles. During the soft-start period, the Zero Cross Detector is active to monitor the voltage across the lower MOSFET while DL is high. If the inductor current reaches zero, the FB comparator’s internal ramp reference is immediately overridden to match the voltage at the FB pin. This soon causes the FB comparator to trip which forces DL to turn off and the next DH on-time will begin. This prevents the inductor current from going too negative which would cause droop in the VOUT startup waveform. The next 30mV step on the internal reference ramp occurs from the new point at the FB pin. Since any of the internal 30mV steps can be overridden by the FB waveform, the startup time is therefore dependent upon operating conditions. This override feature will stop when the FB pin reaches approximately 600mV. At start-up, during the first 32 switching cycles, the over- current threshold is reduced by 50%, to reduce overshoot caused by the first set of switching pulses. MOSFET Gate Drivers The DH and DL drivers are optimized for moderate, high- side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off, and conversely, monitors the DH output and prevents the low- side MOSFET from turning on until DH is fully off. Note: be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Design Procedure Prior to designing a switch mode supply, the input voltage, load current, switching frequency and inductor ripple current must be specified. For notebook systems the maximum input voltage (VIN MAX) is determined by the highest AC adaptor voltage, and the minimum input voltage (VIN MIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Applications Information (continued) |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |