| поискавой системы для электроныых деталей |
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SC471AEVB датащи(PDF) 12 Page - Semtech Corporation |
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SC471AEVB датащи(HTML) 12 Page - Semtech Corporation |
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12 / 27 page ![]() 12 © 2008 Semtech Corp. SC471/SC471A www.semtech.com POWER MANAGEMENT For the case where the down transition is less than 8%, and the load is light such that power-save is active, the Smart Power Save detector will not activate. In this case, with FB already above the 0.75V reference there is no switching activity. DL and DH will remain off, and the output voltage will slowly fall as the output capacitors discharge into the load, see Figure 6. Note: at light loads it can take many msec for the output to fall to the new value. This should have no adverse effect. Many loads such as graphics chipsets can have a minimum load of several hundred mA, which will naturally pull VOUT down to the next level. VOUT FB R1 R2 D0/D1 D0/D1 RTN < 810mV (FB threshold) FB COUT Discharge due to load Initial VOUT Final VOUT VOUT R3/R4 (Smart Psave threshold) Figure 6 The time needed to reach the final voltage is found from the following equation, where COUT is in μF, and LOAD is in Amps: Time (μsec) = COUT • (VINITIAL – VFINAL)/LOAD Note: the preceding equation applies only to the condition where the VOUT downward change is less that the 8% limit for Smart Psave, and also the load is light such that Psave is active. When doing an up transition (from lower to higher VOUT), the G0/G1 change will affect D0/D1 and cause FB to drop below the 0.75V internal reference. This quickly trips the FB comparator regardless of whether psave is active or not, generating a DH on-time and a subsequent DL high time. At the end of the minimum off-time (350nsec), if FB is still below 0.75V then another DH on-time is started, Figure 7. This continues until FB reaches the normal operating point. VOUT FB R1 R2 D0/D1 D0/D1 RTN 750mV (FB threshold) FB DH DL VOUT Final VOUT Initial VOUT R3/R4 Figure 7 If the VOUT change is significant, there can be several consecutive cycles of DH on-time followed by minimum DL time. This can cause a rapid increase in inductor current: typically it only takes a few switching cycles for the induc- tor current to rise up to the Current Limit. At some point the FB voltage will rise up to the 0.75V reference and the DH pulses will cease, but the inductor’s LI2 energy must then flow into the output cap. This can create a significant overshoot as shown in Figure 8. Applications Information (continued) |
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