PCF8576DTSLASH2 datasheet(25/52 Pages) NXP

25 / 52 page

PCF8576D_7

Product data sheet

Rev. 7 — 18 December 2008

25 of 52

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCF8576D device.

An acknowledgement after each byte is asserted only by the PCF8576Ds that are

addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus

access.

7.17 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus.

The commands available to the PCF8576D are deﬁned in Table 7.

[1]

Not used.

All available commands carry a continuation bit C in their most signiﬁcant bit position as

shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to

arrive will also represent a command. If this bit is reset, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data (see Table 8).

Fig 18. Format of command byte

msa833

REST OF OPCODE

MSB

LSB

Table 7.

Deﬁnition of PCF8576D commands

Command

Operation Code

Reference

Bit

mode-set

[1]

Table 9

load-data-pointer

Table 10

device-select

1100A2

Table 11

bank-select

11110I

Table 12

blink-select

1110A

BF1

BF0

Table 13

Table 8.

C bit description

Bit

Symbol

Value

Description

continue bit

last control byte in the transfer; next byte will be regarded

as display data

control bytes continue; next byte will be a command too

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