74LVT_LVTH574_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 11 September 2008

8 of 16

NXP Semiconductors

74LVT574; 74LVTH574

3.3 V octal D-type flip-flop; 3-state

11. Waveforms

Measurement points are given in Table 8

Fig 6.

Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency

001aac445

CP input

Qn output

GND

Measurement points are given in Table 8

with the output load.

Measurement points are given in Table 8

with the output load.

Fig 7.

Output enable time to HIGH-state and output

disable time from HIGH-state

Fig 8.

Output enable time to LOW-state and output

disable time from LOW-state

Qn output

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OE input

GND

GND

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Qn output

OE input

3.0 V

GND

Measurement points are given in Table 8

Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9.

Data setup and hold times

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CP input

Dn input

GND

GND