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MPC5565 Microcontroller Data Sheet, Rev. 2.0

Revision History for the MPC5565 Data Sheet

Freescale Semiconductor

5.2

Changes to Revision 0.0 in Revision 1.0

The following table lists the information that changed in the tables between Rev. 0.0 and 1.0.

Table 30. MPC5565 Changes Between Rev. 0.0 and 1.0

Location

Description of Changes

Table 6 VCR/POR Electrical Specifications:

• Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5

negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions

as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies

fall outside the operating conditions and until the internal POR asserts.

Table 9 DC Electrical Specifications:

• Added (TA = TL to TH) to the table title.

Table 22 Bus Operation Timing:

• External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum

frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow

for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts

allow for 132 MHz system clock + 2% FM.

• Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.

• Specs 7 and 8: Removed from external bus interface: BDIP, OE, and WE/BE[0:3].

• Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.

Table 25 eMIOS Timing:

• Deleted (MTS) from the heading, table, and footnotes.

• Footnote 1: Deleted ‘. . .fSYS = 132 MHz. . .’, ‘. . .VDD33 and VDDSYN = 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF

with SRC = 0b11.’

• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum

eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad

configuration registers (PCR).’

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