MPC5565 datasheet(35/54 Pages) FREESCALE

35 / 54 page

Electrical Characteristics

MPC5565 Microcontroller Data Sheet, Rev. 2.0

Freescale Semiconductor

Figure 12. CLKOUT Timing

CLKOUT positive edge to input

signal invalid (hold time)

External bus interface

ADDR[8:31]

DATA[0:31] 5

RD_WR

TEA 6

tCIH

1.0

—

1.0

—

1.0

—

CLKOUT positive edge to input

signal invalid (hold time)

Calibration bus interface

CAL_ADDR[10:30]

CAL_DATA[0:15]

CAL_RD_WR

CAL_TS

tCCIH

1.0

—

1.0

—

1.0

—

1 EBI timing specified at: V

DDE = 1.6–3.6 V (unless stated otherwise); TA = TL to TH; and CL = 30 pF with DSC = 0b10.

2 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).

82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and

135 MHz parts allow for 132 MHz system clock + 2% FM.

3 The external bus is limited to half the speed of the internal bus.

4 Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).

5 Due to pin limitations, the DATA[16:31] signals are not available on the 324 package.

6 Due to pin limitations, the TEA signal is not available on the 324 package.

7 Due to pin limitations, the WE/BE[2:3] signals are not available on the 324 package.

8 SIU_ECCR[EBTS] = 0 timings are tested and valid at V

DDE = 2.25–3.6 V only; SIU_ECCR[EBTS] = 1 timings are tested and

valid at VDDE = 1.6–3.6 V.

Table 22. Bus Operation Timing1 (continued)

Spec

Characteristic

and

Description

Symbol

External Bus Frequency 2, 3

Unit

Notes

40 MHz

56 MHz

66 MHz

Min.

Max.

Min.

Max.

Min.

Max.

CLKOUT

VDDE ÷ 2

Vol_f

Voh_f

MPC5565 датащи(PDF) 35 Page - Freescale Semiconductor, Inc

MPC5565 датащи(HTML) 35 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

датащи скачать

ссылки URL