PRELIMINARY
CY2DP818-2
1:8 Clock Fanout Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07588 Rev. *A
Revised October 22, 2008
Features
■ Low voltage operation VDD = 3.3V
■ 1:8 fanout
■ Single-input configurable for LVDS, LVPECL, or LVTTL
■ 8 pairs of LVPECL outputs with enable and disable
■ Drives a 50 ohm load
■ Low input capacitance
■ Low output skew
■ Low propagation delay typical (tpd < 4 ns)
■ Industrial versions available
■ Package available include: TSSOP
■ Does not exceed Bellcore 802.3 standards
■ Operation up to 350 MHz and 700 Mbps
Description
This Cypress series of network circuits is produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818-2 fanout buffer features a single
LVDS or a single-ended LVTTL compatible input and eight
LVPECL output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818-2 is ideal for both level translations from
single-ended to LVPECL and for the distribution of LVPECL
based clock signals.
The Cypress CY2DP818-2 has configurable input functions.
The input is user configurable through the Inconfig pin for
single ended or differential input.
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
EN1
EN2
EN3
EN4
EN5
EN6
EN7
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