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CY2DP818-2 датащи(PDF) 4 Page - Cypress Semiconductor

номер детали CY2DP818-2
подробное описание детали  1:8 Clock Fanout Buffer
PDF  9 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DP818-2 датащи(HTML) 4 Page - Cypress Semiconductor

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PRELIMINARY
CY2DP818-2
Document #: 38-07588 Rev. *A
Page 4 of 9
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
DC Supply Voltage
Inputs and VCC
–0.3
4.6
V
VDD
DC Operating Voltage
Outputs
–0.3
VDD + 0.3
V
VIN
DC Input Voltage
Relative to VSS, with or VDD applied
–0.3
VDD + 0.3
V
VOUT
DC Output Voltage
Relative to VSS
–0.3
VDD + 0.9
V
VTT
Output Termination Voltage
VDD ÷ 2V
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating
Ambient
Commercial Functional
0
70
°C
Industrial
Functional
–40
+85
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is
NOT required.
DC Electrical Specifications
3.3V – LVDS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter
Description
Conditions
Min
Typ
Max
Unit
VID
Magnitude of Differential Input Voltage
100
600
mV
VIC
Common Mode of Differential Input
VoltageIVIDI (minimum and maximum)
IVIDI/2
2.4–(IVIDI/2)
V
IIH
Input High Current
VDD = Max.
VIN = VDD
±10
± 20
μA
IIL
Input Low Current
VDD = Max.
VIN = VSS
±10
± 20
μA
3.3V – LVPECL Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter
Description
Conditions
Min
Typ
Max
Unit
VID
Differential Input Voltage p-p
Guaranteed Logic High Level
400
2600
mV
VIH
Input High Voltage
Guaranteed Logic High Level
2.15
2.4
V
VIL
Input Low Voltage
Guaranteed Logic Low Level
1.5
1.8
V
IIH
Input High Current
VDD = Max.
VIN = VDD
–±10
±20
μA
IIL
Input Low Current
VDD = Max.
VIN = VSS
–±10
±20
μA
VCM
Common-mode Voltage
1650
2250
mV
3.3V – LVTTL/LVCMOS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter
Description
Conditions
Min
Typ
Max
Units
VIH
Input High Voltage
Guaranteed Logic High Level
2
V
VIL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
IIH
Input High Current
VDD = Max
VIN = 2.7V
1
μA
IIL
Input Low Current
VDD = Max
VIN = 0.5V
–1
μA
II
Input High Current
VDD = Max, VIN = VDD (Max)
VIK
Clamp Diode Voltage
VDD = Min, IIN = –18 mA
–0.7
–1.2
V
VH
Input Hysteresis[1]
–80
mV
Note
1. Guaranteed but not tested.
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