PRELIMINARY
CY2DP818-2
Document #: 38-07588 Rev. *A
Page 5 of 9
Figure 2. Driver Design
3.3V – LVPECL Output at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOD
Driver Differential Output Voltage p-p
VDD = Min, VIN = VIH or VIL RL = 50 ohm 1000
–
3600
mV
ΔVOC
Driver common-Mode Variation p-p
VDD = Min, VIN = VIH or VIL RL = 50 ohm
–
–
300
mV
Rise Time
Differential 20% to 80%
CL–10 pF RL and CL to
GND
RL = 50 ohm
300
1200
ps
Fall Time
VOH
Output High Voltage
VDD = Min, VIN = VIH or VIL IOH = –12 mA
2.1
–
3.0
V
VOL
Output Low Voltage
VDD = Min, VIN = VIH or VIL
User-defined by VTT RTT.
0.8
–
1.3
V
IOS
Short Circuit Current
VDD = Max, VOUT = GND
–
–
–150
mA
AC Switching Characteristics
(at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C)
Parameter
Description
Conditions
Min
Typ
Max
Unit
tPLH
Propagation Delay – Low to High
VOD = 100
mV
34
5
ns
tPHL
Propagation Delay – High to Low
3
4
5
ns
TPE
Enable (EN) to Functional Operation
–
–
6
ns
TPD
Functional Operation to Disable
–
–
5
ns
tSK(0)
Output Skew: Skew between outputs of the same package (in phase)
–
–
0.2
ns
tSK(p)
Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH)–
0.2
ns
tSK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature, and package type. Same
input signal level and output load.
VID = 100 mV
–
–
1
ns
High Frequency Parametrics
Parameter
Description
Conditions
Min
Typ
Max
Unit
Fmax
Maximum Frequency
VDD = 3.3V
45% to 55% duty cycle
Standard load circuit
–
–
350
MHz
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