AD9522-2SLASHPCBZ datasheet(15/84 Pages) AD

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AD9522-2

Rev. 0 | Page 15 of 84

POWER DISSIPATION

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION, CHIP

Does not include power dissipated in external resistors; all LVDS

outputs terminated with 100 Ω across differential pair; all CMOS

outputs have 10 pF capacitive loading

Power-On Default

0.88

1.0

No clock; no programming; default register values

PLL Locked; One LVDS Output Enabled

0.54

0.63

fREF = 25 MHz; fOUT = 250 MHz; VCO = 2250 MHz; VCO divider = 3;

one LVDS output and output divider enabled; zero delay off;

ICP = 4.8 mA

PLL Locked; One CMOS Output Enabled

0.55

0.66

fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 2250 MHz; VCO divider = 3;

one CMOS output and output divider enabled; zero delay off;

ICP = 4.8 mA

Distribution Only Mode; VCO Divider On;

One LVDS Output Enabled

0.36

0.43

fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVDS output

and output divider enabled; zero delay off

Distribution Only Mode; VCO Divider Off;

One LVDS Output Enabled

0.33

0.4

fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVDS

output and output divider enabled; zero delay off

Maximum Power, Full Operation

1.1

1.3

PLL on; internal VCO = 2250 MHz; VCO divider = 3; all channel

dividers on; 12 LVDS outputs @ 125 MHz; zero delay on

PD Power-Down

PD pin pulled low; does not include power dissipated in

termination resistors

PD Power-Down, Maximum Sleep

PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-

down SYNC, 0x230[2] = 1b; power-down distribution reference,

0x230[1] = 1b

VCP Supply

2.3

PLL operating; typical closed-loop configuration

POWER DELTAS, INDIVIDUAL FUNCTIONS

Power delta when a function is enabled/disabled

VCO Divider On/Off

VCO divider not used

REFIN (Differential) Off

Delta between reference input off and differential reference

input mode

REF1, REF2 (Single-Ended) On/Off

Delta between reference inputs off and one single-ended

reference enabled; double this number if both REF1 and REF2

are powered up

VCO On/Off

Internal VCO disabled; CLK input selected

PLL Dividers and Phase Detector On/Off

PLL off to PLL on, normal operation; no reference enabled

LVDS Channel

118

146

No LVDS output on to one LVDS output on; channel divider set to 1

LVDS Driver

Second LVDS output turned on, same channel

CMOS Channel

120

154

No CMOS output on to one CMOS output on; channel divider

set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading

CMOS Driver On/Off

Additional CMOS outputs within the same channel turned on

Channel Divider Enabled

Delta between divider bypassed (divide-by-1) and divide-by-2 to

divide-by-32

Zero Delay Block On/Off

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