AD9522-2SLASHPCBZ datasheet(48/84 Pages) AD

48 / 84 page

AD9522-2

Rev. 0 | Page 48 of 84

CMOS Output Drivers

The user can also individually configure each LVDS output as a

pair of CMOS outputs, which provides up to 24 CMOS outputs.

When an output is configured as CMOS, CMOS Output A

and CMOS Output B are automatically turned on. For a given

differential pair, either CMOS Output A or Output B can be

turned on or off independently. The user can also select the

relative polarity of the CMOS outputs for any combination of

inverting and noninverting (see Register 0x0F0 to Register 0x0FB).

The user can power down each CMOS output as needed to save

power. The CMOS output power-down is individually controlled

by the CMOS configuration bits (0x0F0[6:5] to 0x0FB[6:5]). The

CMOS driver is in tristate when it is powered down.

OUT1/

OUT1

Figure 55. CMOS Equivalent Output Circuit

RESET MODES

The AD9522 has a power-on reset (POR) and several other

ways to apply a reset condition to the chip.

Power-On Reset

During chip power-up, a power-on reset pulse is issued when

VS reaches ~2.6 V (<2.8 V) and restores the chip either to the

setting stored in EEPROM (with the EEPROM pin = 1) or to

the on-chip setting (with the EEPROM pin = 0). At power-on,

the AD9522 also executes a SYNC operation, which brings the

outputs into phase alignment according to the default settings.

The output drivers are held in sync for the duration of the

internally generated power-up sync timer (~70 ms). The

outputs begin to toggle after this period.

Hardware Reset via the RESET Pin

RESET, a hard reset (an asynchronous hard reset is executed by

briefly pulling RESET low), restores the chip either to the setting

stored in EEPROM (the EEPROM pin = 1) or to the on-chip

setting (the EEPROM pin = 0). A hard reset also executes a

SYNC operation, which brings the outputs into phase alignment

according to the default settings. When EEPROM is inactive

(the EEPROM pin = 0), it takes ~2 μs for the outputs to begin

toggling after RESET is issued. When EEPROM is active (the

EEPROM pin = 1), it takes ~20 ms for the outputs to toggle after

RESET is brought high.

Soft Reset via the Serial Port

The serial port control register allows for a soft reset by setting

Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,

the chip enters a soft reset mode and restores the chip either to

the setting stored in EEPROM (the EEPROM pin = 1) or to the

on-chip setting (the EEPROM pin = 0), except for Register 0x000.

Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000

retains its previous value prior to reset. During the internal reset,

the outputs hold static. These bits are self-clearing. However, the

self-clearing operation does not complete until an additional

serial port SCLK cycle, and the AD9522 is held in reset until

that happens.

Soft Reset to Settings in EEPROM When EEPROM Pin = 0 via

the Serial Port

The serial port control register allows the chip to be reset to

settings in EEPROM when the EEPROM pin = 1 via 0xB02[1].

This bit is self-clearing. This bit does not have any effect when

the EEPROM pin = 0. It takes ~20 ms for the outputs to begin

toggling after the Soft_EEPROM register is cleared.

POWER-DOWN MODES

Chip Power-Down via PD

The AD9522 can be put into a power-down condition by pulling

the PD pin low. Power-down turns off most of the functions and

currents inside the AD9522. The chip remains in this power-down

state until PD is brought back to logic high. When taken out of

power-down mode, the AD9522 returns to the settings programmed

in its registers prior to the power-down, unless the registers are

changed by new programming while the PD pin is held low.

Powering down the chip shuts down the currents on the chip.

Because this is not a complete power-down, it can be called

sleep mode. The AD9522 contains special circuitry to prevent

runt pulses on the outputs when the chip is entering or exiting

sleep mode.

When the AD9522 is in a PD power-down, the chip is in the

following state:

•

The PLL is off (asynchronous power-down).

•

The VCO is off.

•

The CLK input buffer is off, but the CLK input dc bias

circuit is on.

•

In differential mode, the reference input buffer is off, but

the dc bias circuit is still on.

•

In singled-ended mode, the reference input buffer is off,

and the dc bias circuit is off.

•

All dividers are off.

•

All CMOS outputs are tristated.

•

All LVDS outputs are in power-down (high impedance)

mode.

•

The serial control port is active, and the chip responds to

commands.

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