AD9522-2SLASHPCBZ datasheet(34/84 Pages) AD

34 / 84 page

AD9522-2

Rev. 0 | Page 34 of 84

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs and

tells the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the internal VCO through the LF pin (or the

tuning pin of an external VCO) to move the VCO frequency up

or down. The CP can be set (0x010[3:2]) for high impedance

(allows holdover operation), for normal operation (attempts to

lock the PLL loop), for pump-up, or for pump-down (test modes).

The CP current is programmable in eight steps from (nominally)

0.6 mA to 4.8 mA. The exact value of the CP current LSB is set

by the CPRSET resistor, which is nominally 5.1 kΩ.

On-Chip VCO

The AD9522 includes an on-chip VCO covering the frequency

range shown in Table 2. Achieving low VCO phase noise was a

priority in the design of the VCO.

To tune over the wide range of frequencies covered by this

VCO, tuning ranges are used. The calibration procedure selects

the correct range for the desired VCO frequency. See the VCO

Calibration section for additional information.

The on-chip VCO is powered by an on-chip, low dropout (LDO),

linear voltage regulator. The LDO provides some isolation of

the VCO from variations in the power supply voltage level.

The BYPASS pin should be connected to ground by a 220 nF

capacitor to ensure stability. This LDO employs the same

technology used in the anyCAP® line of regulators from Analog

Devices, Inc., making it insensitive to the type of capacitor used.

Driving an external load from the BYPASS pin is not supported.

When using an external VCO/VCXO, the BYPASS and LF pins

should be left floating. This configuration is shown in Figure 42.

PLL External Loop Filter

When using the internal VCO, the external loop filter should be

referenced to the BYPASS pin for optimal noise and spurious

performance. An example of an external loop filter for a PLL

that uses the internal VCO is shown in Figure 41. A loop filter

must be calculated for each desired PLL configuration. The values

of the components depend upon the VCO frequency, the KVCO,

the PFD frequency, the CP current, the desired loop bandwidth,

and the desired phase margin. The loop filter affects the phase

noise, the loop settling time, and the loop stability. A basic

knowledge of PLL theory is helpful for understanding loop filter

design. ADIsimCLK can help with the calculation of a loop

filter according to the application requirements.

When using an external VCO, the external loop filter should be

referenced to ground. An example of an external loop filter for a

PLL using an external VCO is shown in Figure 42.

VCO

CHARGE

PUMP

BYPASS

CBP = 220nF

AD9522

Figure 41. Example of External Loop Filter for a PLL Using the Internal VCO

CLK/CLK

EXTERNAL

VCO/VCXO

CHARGE

PUMP

AD9522

Figure 42. Example of External Loop Filter for a PLL Using an External VCO

PLL Reference Inputs

The AD9522 features a flexible PLL reference input circuit that

allows a fully differential input, two separate single-ended inputs,

or a 16.62 MHz to 33.33 MHz crystal oscillator with an on-chip

maintaining amplifier. An optional reference clock doubler

can be used to double the PLL reference frequency. The input

frequency range for the reference inputs is specified in Table 2.

Both the differential and the single-ended inputs are self-biased,

allowing for easy ac coupling of input signals. To increase isolation

and reduce power, each single-ended input can be independently

powered down.

Either a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential input and the single-ended inputs share two pins,

REFIN (REF1) and REFIN (REF2). The desired reference input

type is selected and controlled by 0x01C (see

and

Table 48

Table 52

In single-ended mode, the AD9522 features a dc offset option.

Setting 0x018[7] to 1b shifts the dc offset bias point down 140 mV.

This option eliminates the risk of the reference inputs chattering

when they are ac-coupled and the reference clock disappears.

When using the reference switchover, the single-ended reference

inputs should be dc-coupled CMOS levels (with the AD9522 dc

offset feature disabled). Alternatively, the inputs can be ac-coupled,

and the dc offset feature can be enabled. The user should keep in

mind, however, that the minimum input amplitude for the

reference inputs is greater when the dc offset is turned on.

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly to prevent chattering of

the input buffer when the reference is slow or missing. The

specification for this voltage level can be found in Table 2.

The input hysteresis increases the voltage swing required of

the driver to overcome the offset.

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