AD9522-2 datasheet(9/84 Pages) AD

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AD9522-2

Rev. 0 | Page 9 of 84

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVDS ADDITIVE PHASE NOISE

Distribution section only; does not include PLL and VCO

CLK = 1.6 GHz, Output = 800 MHz

Input slew rate > 1 V/ns

Divider = 2

@ 10 Hz Offset

−100

dBc/Hz

@ 100 Hz Offset

−110

dBc/Hz

@ 1 kHz Offset

−117

dBc/Hz

@ 10 kHz Offset

−126

dBc/Hz

@ 100 kHz Offset

−134

dBc/Hz

@ 1 MHz Offset

−137

dBc/Hz

@ 10 MHz Offset

−147

dBc/Hz

@ 100 MHz Offset

−148

dBc/Hz

CLK = 1 GHz, Output = 200 MHz

Input slew rate > 1 V/ns

Divider = 5

@ 10 Hz Offset

−111

dBc/Hz

@ 100 Hz Offset

−123

dBc/Hz

@ 1 kHz Offset

−132

dBc/Hz

@ 10 kHz Offset

−141

dBc/Hz

@ 100 kHz Offset

−146

dBc/Hz

@ 1 MHz Offset

−150

dBc/Hz

>10 MHz Offset

−156

dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

Distribution section only; does not include PLL and VCO

CLK = 1 GHz, Output = 500 MHz

Input slew rate > 1 V/ns

Divider = 2

@ 10 Hz Offset

−102

dBc/Hz

@ 100 Hz Offset

−114

dBc/Hz

@ 1 kHz Offset

−122

dBc/Hz

@ 10 kHz Offset

−129

dBc/Hz

@ 100 kHz Offset

−135

dBc/Hz

@ 1 MHz Offset

−140

dBc/Hz

>10 MHz Offset

−150

dBc/Hz

CLK = 1 GHz, Output = 50 MHz

Input slew rate > 1 V/ns

Divider = 20

@ 10 Hz Offset

−125

dBc/Hz

@ 100 Hz Offset

−136

dBc/Hz

@ 1 kHz Offset

−144

dBc/Hz

@ 10 kHz Offset

−152

dBc/Hz

@ 100 kHz Offset

−157

dBc/Hz

@ 1 MHz Offset

−160

dBc/Hz

>10 MHz Offset

−164

dBc/Hz

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