AD9522-2 datasheet(35/84 Pages) AD

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AD9522-2

Rev. 0 | Page 35 of 84

The differential reference input receiver is powered down when

it is not selected or when the PLL is powered down. The single-

ended buffers power down when the PLL is powered down or

when their respective individual power-down registers are set.

When the differential mode is selected, the single-ended inputs

are powered down.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by

a single-ended signal, the unused side (REFIN) should be

decoupled via a suitable capacitor to a quiet ground.

shows the equivalent circuit of REFIN.

Figure 43

REF1

REF2

REFIN

150Ω

10kΩ

12kΩ

10kΩ

REFIN

85kΩ

Figure 43. REFIN Equivalent Circuit for Non-XTAL Mode

Crystal mode is nearly identical to differential mode. The user

enables a maintaining amplifier by setting the enable XTAL

OSC bit, and putting a series resonant, AT fundamental cut

crystal across the REFIN/REFIN pins.

Reference Switchover

The AD9522 supports dual single-ended CMOS inputs, as well

as a single differential reference input. In the dual single-ended

reference mode, the AD9522 supports automatic and manual

PLL reference clock switching between REF1 (on Pin REFIN)

and REF2 (on Pin REFIN). This feature supports networking

and other applications that require hitless switching of redundant

references. When used in conjunction with the automatic

holdover function, the AD9522 can achieve a worst-case

reference input switchover with an output frequency disturbance

as low as 10 ppm.

There are several configurable modes of reference switchover.

The switchover can be performed manually or automatically.

Manual switchover is performed either through Register 0x01C

or by using the REF_SEL pin. The automatic switchover occurs

when REF1 disappears. A switchover deglitch feature ensures

which the PLL does not receive rising edges that are far out of

alignment with the newly selected reference.

There are two automatic reference switchover modes (0x01C):

•

Prefer REF1. Switch from REF1 to REF2 when REF1

disappears. Return to REF1 from REF2 when REF1 returns.

•

Stay on REF2. Automatically switch to REF2 if REF1

disappears but do not switch back to REF1 if it reappears.

The reference can be set back to REF1 manually at an

appropriate time.

In automatic mode, REF1 is monitored by REF2. If REF1

disappears (two consecutive falling edges of REF2 without an

edge transition on REF1), REF1 is considered missing. On the

next subsequent rising edge of REF2, REF2 is used as the reference

clock to the PLL. If 0x01C[3] = 0b (default), when REF1 returns

(four rising edges of REF1 without two falling edges of REF2

between the REF1 edges), the PLL reference switches back to

REF1. If 0x01C[3] = 1b, the user can control when to switch

back to REF1. This is done by programming the part to manual

reference select mode (0x01C[4] = 0b) and by ensuring that the

registers and/or the REF_SEL pin are set to select the desired

reference. Automatic mode can be reenabled when REF1 is

reselected.

Manual switchover requires the presence of a clock on the reference

input being switched to or that the deglitching feature be

disabled (0x01C[7]).

Reference Divider R

The reference inputs are routed to the reference divider, R. R (a

14-bit counter) can be set to any value from 0 to 16,383 by writing

to 0x011 and 0x012. (Both R = 0 and R = 1 give divide-by-1.) The

output of the R divider goes to one of the PFD inputs to be

compared with the VCO frequency divided by the N divider.

The frequency applied to the PFD must not exceed the maximum

allowable frequency, which depends on the antibacklash pulse

setting (see Table 2).

The R divider has its own reset. The R divider can be reset using

the shared reset bit of the R, A, and B counters. It can also be

reset by a SYNC operation.

VCO/VCXO Feedback Divider N: P, A, B, R

The N divider is a combination of a prescaler (P) and two counters,

A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

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