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AD9520-5/PCBZ датащи(PDF) 28 Page - Analog Devices |
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AD9520-5/PCBZ датащи(HTML) 28 Page - Analog Devices |
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28 / 80 page ![]() AD9520-5 Rev. 0 | Page 28 of 80 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that allows for an external input up to 2400 MHz (see ). The maximum frequency that can be applied to the channel dividers is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. Table 3 When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency <2400 MHz. In this configuration, the external VCO/VCXO feeds directly into the prescaler. The register settings shown in Table 22 are the default values of these registers at power-up or after a reset operation. Table 22. Default Register Settings for Clock Distribution Mode Register Description 0x010[1:0] = 01b PLL asynchronous power-down (PLL off ) 0x1E0[2:0] = 000b Set VCO divider = 2 0x1E1[0] = 0b Use the VCO divider When using the internal PLL with an external VCO, the PLL must be turned on. Table 23. Settings When Using an External VCO Register Description 0x010[1:0] = 00b PLL normal operation (PLL on) 0x010 to 0x01E PLL settings; select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 24. Setting the PFD Polarity Register Description 0x010[7] = 0b PFD polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b PFD polarity negative (higher control voltage produces lower frequency) |
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