M38041FFHKP datasheet(355/387 Pages) RENESAS

355 / 387 page

3-65

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.5 Control registers

Fig. 3.5.24 Structure of Timer XY mode register

Timer XY mode register

b7 b6 b5 b4 b3 b2 b1 b0

Timer XY mode register

(TM: address 002316)

Name

Functions

At reset R W

Refer to Table 3.5.1

Timer X operating

mode bits

Timer Y operating

mode bits

0: Count start

1: Count stop

Refer to Table 3.5.1

0: Count start

1: Count stop

b5 b4

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width

measurement mode

b1 b0

0 0: Timer mode

0 1: Pulse output mode

1 0: Event counter mode

1 1: Pulse width

measurement mode

Timer Y count stop

bit

CNTR1 active edge

switch bit

Timer X count stop

bit

CNTR0 active edge

switch bit

Timer X/Timer Y operation modes

Timer mode

Pulse output mode

Event counter mode

Pulse width measurement mode

CNTR0/CNTR1 active edge switch bit (bits 2 and 6 of address 002316) contents

“0” CNTR0/CNTR1 interrupt request occurrence: Falling edge

; No influence to timer count

“1” CNTR0/CNTR1 interrupt request occurrence: Rising edge

; No influence to timer count

“0” Pulse output start: Beginning at “H” level

CNTR0/CNTR1 interrupt request occurrence: Falling edge

“1” Pulse output start: Beginning at “L” level

CNTR0/CNTR1 interrupt request occurrence: Rising edge

“0” Timer X/Timer Y: Rising edge count

CNTR0/CNTR1 interrupt request occurrence: Falling edge

“1” Timer X/Timer Y: Falling edge count

CNTR0/CNTR1 interrupt request occurrence: Rising edge

“0” Timer X/Timer Y: “H” level width measurement

CNTR0/CNTR1 interrupt request occurrence: Falling edge

“1” Timer X/Timer Y: “L” level width measurement

CNTR0/CNTR1 interrupt request occurrence: Rising edge

Table 3.5.1 CNTR0/CNTR1 active edge switch bit function

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