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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7733 датащи(PDF) 378 Page - Renesas Technology Corp |
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7733 датащи(HTML) 378 Page - Renesas Technology Corp |
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378 / 940 page  CLOCK GENERATING CIRCUIT 7733 Group User’s Manual 14–15 14.3 Clock control 14.3.4 Clock prescaler reset The clock prescaler, which divides a sub clock by 32, is reset by writing “1” to the clock prescaler reset bit (bit 7 at address 6F16). By this function, the count source (fC32) error immediately after the clock timer starts counting can be held down. Figure 14.3.10 shows the operation timing of the clock prescaler and timer B2. Figure 14.3.10 Operation timing of clock prescaler and timer B2 Clock prescaler reset bit write pulse XCIN Clock timer clock source fC32 Timer B2 count value Timer B2 count start flag XCIN divided by 31 (Note) n (Set value) n—1 The above is applied when the main clock is selected as the system clock, in other words, when the system clock selection bit (CM3) = “0.” Note: Only in this period, XCIN divided by 31 is selected. After this period, XCIN divided by 32 is selected. XCIN divided by 32 |
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