4501 datasheet(46/212 Pages) RENESAS

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FUNCTION BLOCK OPERATIONS

1-34

Rev.2.01

Feb 07, 2005

4501 Group

HARDWARE

REJ09B0192-0201

Q13

Q12

A/D control register Q1

A/D operation mode selection bit

Not used

Analog input pin selection bits

at reset : 00002

at RAM back-up : state retained

Q11

A/D conversion mode

Comparator mode

This bit has no function, but read/write is enabled.

Selected pins

AIN0

AIN1

Not available

Note: “R” represents read enabled, and “W” represents write enabled.

Q10

(1) Operating at A/D conversion mode

The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”

(2) Successive comparison register AD

10-bit digital data format. The contents of the high-order 8 bits of

this register can be stored in register B and register A with the

TABAD instruction. The contents of the low-order 2 bits of this reg-

ister can be stored into the high-order 2 bits of register A with the

TALA instruction. However, do not execute these instructions dur-

ing A/D conversion.

When the contents of register AD is n, the logic value of the com-

parison voltage Vref generated from the built-in DA converter can

be obtained with the reference voltage VDD by the following for-

mula:

Logic value of comparison voltage Vref

Vref =

✕ n

n: The value of register AD (n = 0 to 1023)

VDD

1024

R/W

Table 12 A/D control registers

(3) A/D conversion completion flag (ADF)

A/D conversion completion flag (ADF) is set to “1” when A/D con-

version completes. The state of ADF flag can be examined with the

skip instruction (SNZAD). Use the interrupt control register V2 to

select the interrupt or the skip instruction.

The ADF flag is cleared to “0” when the interrupt occurs or when

the next instruction is skipped with the skip instruction.

(4) A/D conversion start instruction (ADST)

A/D conversion starts when the ADST instruction is executed. The

conversion result is automatically stored in the register AD.

(5) A/D control register Q1

log input pins.

Q11

Q10

(6) Operation description

A/D conversion is started with the A/D conversion start instruction

(ADST). The internal operation during A/D conversion is as follows:

➀ When the A/D conversion starts, the register AD is cleared to

“00016.”

➁ Next, the topmost bit of the register AD is set to “1,” and the

comparison voltage Vref is compared with the analog input volt-

age VIN.

➂ When the comparison result is Vref < VIN, the topmost bit of the

Vref > VIN, it is cleared to “0.”

The 4501 Group repeats this operation to the lowermost bit of the

version stops after 62 machine cycles (46.5

µs when f(XIN) = 4.0

MHz in high-speed mode) from the start, and the conversion result

is stored in the register AD. An A/D interrupt activated condition is

satisfied and the ADF flag is set to “1” as soon as A/D conversion

completes (Figure 29).

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