4501 datasheet(39/212 Pages) RENESAS

39 / 212 page

1-27

4501 Group

HARDWARE

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

FUNCTION BLOCK OPERATIONS

Fig. 22 Timers structure

16-bit timer (WDT)

116

Instruction clock

WDF2

ORCLK

XIN

1/4

1/16

W13

W12

Division circuit

divided by 8

divided by 4

divided by 2

P12/CNTR

P12 output

W60

W23

(TR1AB)

T1F

T2F

(TAB1)

W11

W21,W20

1/2

W61

1/2

(T2AB)

(TAB2)

(TAB1)

(TAB2)

(Note 2)

T1AB

MR3, MR2

W10

I12

I11

P13/INT

(Note 1)

I10

W22

Timer 1 underflow signal

I13

WEF

Reset signal

(Note 5)

DWDT instruction

WRST instruction

(Note 4)

WDF1

WRST instruction

(Note 3)

Timer 1 (8)

Timer 1

interrupt

Reload register R1 (8)

Timer 2 (8)

Reload register R2 (8)

Timer 2

interrupt

Data is set automatically from each reload

(auto-reload function)

Notes 1: Timer 1 count start synchronous circuit is set

by the valid edge of P13/INT pin selected by

bits 1 (I11) and 2 (I12) of register I1.

2: Count source is stopped by clearing to “0.”

3: When the WRST instruction is executed at

WDF1 flag = “1,” WDF1 flag is cleared to “0”

and the next instruction is skipped.

When the WRST instruction is executed at

WDF1 flag = “0,” skip is not executed.

4: When the DWDT and WRST instructions are

executed continuously, WEF flag is cleared to

“0” and reset by watchdog timer is not executed.

5: The WEF flag is set to “1” at system reset or

RAM back-up mode.

Instruction clock

Internal clock

generating circuit

(divided by 3)

Prescaler

One-sided edge

detection circuit

Both edges

detection circuit

Falling

Rising

Clock

generation

circuit

System clock

Timer 1 underflow signal

Timer 2 underflow signal

Reset signal

Watchdog

reset signal

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