SH7263 datasheet(21/1862 Pages) RENESAS

21 / 1862 page

Rev. 2.00 Mar. 14, 2008 Page xxi of xxxiv

REJ09B0290-0200

17.7.5 Note on the States of Bits MST and TRN when Arbitration is Lost..................... 865

Section 18 Serial Sound Interface (SSI) ............................................................867

18.1

Features.............................................................................................................................. 867

18.2

Input/Output Pins ...............................................................................................................870

18.3

Register Description........................................................................................................... 871

18.3.1 Control Register (SSICR) ..................................................................................... 872

18.3.2 Status Register (SSISR) ........................................................................................ 878

18.3.3 Transmit Data Register (SSITDR)........................................................................ 883

18.3.4 Receive Data Register (SSIRDR) ......................................................................... 883

18.4

Operation Description ........................................................................................................ 884

18.4.1 Bus Format............................................................................................................ 884

18.4.2 Non-Compressed Modes....................................................................................... 885

18.4.3 Operation Modes................................................................................................... 895

18.4.4 Transmit Operation ............................................................................................... 896

18.4.5 Receive Operation................................................................................................. 899

18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 902

18.4.7 Serial Bit Clock Control........................................................................................ 903

18.5

Usage Notes ....................................................................................................................... 904

18.5.1 Limitations from Overflow during Receive DMA Operation............................... 904

Section 19 Controller Area Network (RCAN-TL1) ..........................................905

19.1

Summary............................................................................................................................ 905

19.1.1 Overview............................................................................................................... 905

19.1.2 Scope..................................................................................................................... 905

19.1.3 Audience ............................................................................................................... 905

19.1.4 References............................................................................................................. 905

19.1.5 Features................................................................................................................. 906

19.2

Architecture ....................................................................................................................... 907

19.3

Programming Model - Overview ....................................................................................... 911

19.3.1 Memory Map ........................................................................................................ 911

19.3.2 Mailbox Structure ................................................................................................. 913

19.3.3 RCAN-TL1 Control Registers .............................................................................. 930

19.3.4 RCAN-TL1 Mailbox Registers............................................................................. 951

19.3.5 Timer Registers..................................................................................................... 966

19.4

Application Note................................................................................................................980

19.4.1 Test Mode Settings ............................................................................................... 980

19.4.2 Configuration of RCAN-TL1 ............................................................................... 982

19.4.3 Message Transmission Sequence.......................................................................... 987

19.4.4 Message Receive Sequence ................................................................................ 1001

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