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SH7263 датащи(PDF) 86 Page - Renesas Technology Corp

номер детали SH7263
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1862 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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SH7263 датащи(HTML) 86 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Mar. 14, 2008 Page 52 of 1824
REJ09B0290-0200
2.3.2
Addressing Modes
Addressing modes and effective address calculation are as follows:
Table 2.8
Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Register direct
Rn
The effective address is register Rn. (The operand
is the contents of register Rn.)
—
Register indirect @Rn
The effective address is the contents of register Rn.
Rn
Rn
Rn
Register indirect
with post-
increment
@Rn+
The effective address is the contents of register Rn.
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
1/2/4
+
Rn + 1/2/4
Rn
(After
instruction
execution)
Byte:
Rn + 1
→ Rn
Word:
Rn + 2
→ Rn
Longword:
Rn + 4
→ Rn
Register indirect
with pre-
decrement
@-Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
1/2/4
Rn – 1/2/4
–
Rn – 1/2/4
Byte:
Rn – 1
→ Rn
Word:
Rn – 2
→ Rn
Longword:
Rn – 4
→ Rn
(Instruction is
executed with
Rn after this
calculation)



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