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SH7263 датащи(PDF) 49 Page - Renesas Technology Corp

номер детали SH7263
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1862 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7263 датащи(HTML) 49 Page - Renesas Technology Corp

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Section 1 Overview
Rev. 2.00 Mar. 14, 2008 Page 15 of 1824
REJ09B0290-0200
Classification
Symbol
I/O
Name
Function
NMI
I
Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix it high when not in use.
IRQ7 to IRQ0
I
Interrupt requests
7 to 0
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
PINT7 to PINT0 I
Interrupt requests
7 to 0
Maskable interrupt request pins.
Only level-input detection can be
selected.
Interrupts
IRQOUT
O
Interrupt request
output
Indicates that an interrupt has
occurred, enabling external devices
to be informed of an interrupt
occurrence even while the bus
mastership is released.
Address bus
A25 to A0
O
Address bus
Outputs addresses.
Data bus
D31 to D0
I/O
Data bus
Bidirectional data bus.
Bus control
CS7 to CS0
O
Chip select 7 to 0 Chip-select signals for external
memory or devices.
RD
O
Read
Indicates that data is read from an
external device.
RD/
WR
O
Read/write
Read/write signal.
BS
O
Bus start
Bus-cycle start signal.
AH
O
Address hold
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
FRAME
O
FRAME signal
Connected to the
FRAME signal in
the burst MPX-I/O interface.
WAIT
I
Wait
Inserts a wait cycle into the bus
cycles during access to the external
space.
WE0
O
Byte select
Indicates a write access to bits 7 to 0
of data of external memory or
device.



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