R8C13 datasheet(39/224 Pages) RENESAS

39 / 224 page

Rev.1.20

Jan 27, 2006

page 28 of 205

REJ09B0111-0120

R8C/13 Group

5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt

A voltage detection interrupt is generated when the input voltage at the VCC pin rises to Vdet or more

or drops below Vdet if all of the following conditions hold true in stop mode.

• The VC27 bit in the VCR2 register is set to “1” (voltage detection circuit enabled)

• The D40 bit in the D4INT register is set to “1” (voltage detection interrupt enabled)

• The D41 bit in the D4INT register is set “1” (digital filter disabled mode)

• The D46 bit in the D4INT register is set “0” (voltage detection interrupt selected)

The voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscil-

lation stop detection interrupt.

The D42 bit in the D4INT register becomes “1” when passing through Vdet is detected after the volt-

age inputted to the VCC pin is up or down.

A voltage detection interrupt request is generated when the D42 bit changes state from “0” to “1”. The

D42 bit needs to be set to “0” in a program.

Table 5.3 lists the voltage detection interrupt request generation conditions to get out of stop mode.

Table 5.3 Voltage Detection Interrupt Request Generation Conditions to get out of Stop mode

VC27 bit

D40 bitD42 bit

D41 bit

VC13 bit

Operation mode

D46 bit

From 0 to 1

From 1 to 0

Stop mode

NOTES:

1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to Chapter 6, "Clock

Generation Circuit.")

2. Refer to Figure 5.14, "Operation Example of Voltage Detection Interrupt Generation Circuit" for interrupt generation

timing.

D47 bit

0 or 1

5.4 Voltage Detection Circuit

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