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7534 датащи(PDF) 59 Page - Renesas Technology Corp |
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7534 датащи(HTML) 59 Page - Renesas Technology Corp |
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59 / 221 page ![]() HARDWARE 7534 Group Rev.3.00 Oct 23, 2006 page 46 of 55 REJ09B0178-0300 Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 52 shows a timing chart after an interrupt occurs, and Figure 53 shows the time up to execution of the interrupt processing routine. Fig. 52 Timing chart after an interrupt occurs Fig. 53 Time up to execution of the interrupt processing routine : CPU operation code fetch cycle : Vector address of each interrupt : Jump destination address of each interrupt : “0016” or “0116” SYNC BL, BH AL, AH SPS Data bus Not used PCH PCL PS AL AH Address bus S, SPS S-2, SPS S-1, SPS PC BL BH AL, AH SYNC RD WR φ Generation of interrupt request Main routine Interrupt processing routine 7 to 14 cycles (At performing 6.0 MHz, in double-speed mode, 1.17 µs to 2.34 µs) 2 cycles 5 cycles Start of interrupt processing 0 to 7 cycles Waiting time for post-processing of pipeline Stack push and Vector fetch FUNCTIONAL DESCRIPTION SUPPLEMENT |
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