SH7032 datasheet(21/687 Pages) RENESAS

21 / 687 page

Rev. 7.00 Jan 31, 2006 page xxi of xxvi

13.4 SCI Interrupt Sources and the DMAC .............................................................................. 407

13.5 Usage Notes ...................................................................................................................... 407

Section 14 A/D Converter................................................................................................. 411

14.1 Overview........................................................................................................................... 411

14.1.1 Features................................................................................................................ 411

14.1.2 Block Diagram ..................................................................................................... 412

14.1.3 Configuration of Input Pins.................................................................................. 413

14.1.4 Configuration of A/D Registers ........................................................................... 414

14.2 Register Descriptions ........................................................................................................ 414

14.2.1 A/D Data Registers A–D (ADDRA–ADDRD).................................................... 414

14.2.2 A/D Control/Status Register (ADCSR)................................................................ 415

14.2.3 A/D Control Register (ADCR)............................................................................. 417

14.3 CPU Interface.................................................................................................................... 418

14.4 Operation........................................................................................................................... 420

14.4.1 Single Mode (SCAN = 0)..................................................................................... 420

14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 422

14.4.3 Input Sampling Time and A/D Conversion Time ................................................ 424

14.4.4 A/D Conversion Start by External Trigger Input ................................................. 425

14.5 Interrupts and DMA Transfer Requests ............................................................................ 425

14.6 Definitions of A/D Conversion Accuracy ......................................................................... 426

14.7 A/D Converter Usage Notes.............................................................................................. 427

14.7.1 Setting Analog Input Voltage............................................................................... 427

14.7.2 Handling of Analog Input Pins ............................................................................ 427

14.7.3 Switchover between Analog Input and General Port Functions........................... 428

Section 15 Pin Function Controller (PFC) ................................................................... 429

15.1 Overview........................................................................................................................... 429

15.2 Register Configuration ...................................................................................................... 431

15.3 Register Descriptions ........................................................................................................ 431

15.3.1 Port A I/O Register (PAIOR)............................................................................... 431

15.3.2 Port A Control Registers (PACR1 and PACR2) .................................................. 432

15.3.3 Port B I/O Register (PBIOR) ............................................................................... 437

15.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 438

15.3.5 Column Address Strobe Pin Control Register (CASCR) ..................................... 444

Section 16 I/O Ports (I/O) ................................................................................................. 447

16.1 Overview........................................................................................................................... 447

16.2 Port A................................................................................................................................ 447

16.2.1 Register Configuration......................................................................................... 447

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