SH7032 datasheet(73/687 Pages) RENESAS

73 / 687 page

Section 2 CPU

Rev. 7.00 Jan 31, 2006 page 47 of 658

REJ09B0272-0700

Reset State: In the reset state the CPU is reset. This occurs when the

RES pin level goes low.

When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur.

When turning on the power, be sure to carry out a power-on reset.

In a power-on reset, all CPU internal states and on-chip supporting module registers are initialized.

In a manual reset, all CPU internal states and on-chip supporting module registers, with the

exception of the bus state controller (BSC) and pin function controller (PFC), are initialized. In a

manual reset, the BSC is not initialized, so refresh operations will continue.

Exception Handling State: Exception handling is a transient state that occurs when the CPU’s

processing state flow is altered by exception handling sources such as resets or interrupts.

In a reset, the initial values of the program counter PC (execution start address) and stack pointer

SP are fetched from the exception vector table and stored; the CPU then branches to the execution

start address and execution of the program begins.

For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status

from the exception vector table; the CPU then branches to that address and the program starts

executing, thereby entering the program execution state.

Program Execution State: In the program execution state, the CPU sequentially executes the

program.

Power-Down State: In the power-down state, CPU operation halts and power consumption

decreases. The SLEEP instruction places the CPU in the power-down state. This state has two

modes: sleep mode and standby mode.

Bus-Released State: In the bus-released state, the CPU releases the bus to the device that has

requested it.

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