SH7032 datasheet(86/687 Pages) RENESAS

номер детали	SH7032

подробное описание детали	32-Bit RISC Microcomputer

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Section 4 Exception Handling

Rev. 7.00 Jan 31, 2006 page 60 of 658

REJ09BX0272-0700

Table 4.7

Interrupt Priority Rankings

Type

Priority

Comments

NMI

Fixed and unmaskable

User break

Fixed

IRQ and on-chip supporting

modules

0–15

Set in interrupt priority level registers A–E

(IPRA–IPRE)

4.4.3

Interrupt Exception Handling

When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always

accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the

interrupt mask bits (I3–I0) of SR.

When an interrupt is accepted, interrupt exception handling begins. In the interrupt exception

handling sequence, the SR and PC values are pushed onto the stack, and the priority level of the

accepted interrupt is copied to the interrupt mask level bits (I3–I0) in SR. In NMI exception

handling, the priority ranking is 16 but the value 15 (H'F) is stored in I3–I0. The exception

handling routine start address for the accepted interrupt is fetched from the exception vector table

and the program branches to that address and starts executing. For further information on

interrupts, see section 5.4, Interrupt Operation.

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