H8S2245 datasheet(231/818 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 189 of 772

REJ09B0355-0300

Table 7.2 outlines the functions of the DTC.

Table 7.2

DTC Functions

Address Registers

Transfer Mode

Activation Source

Transfer

Source

Transfer

Destination

• Normal mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 Up to 65,536 transfers possible

• Repeat mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 After the specified number of transfers

(1 to 256), the initial state resumes and

operation continues

• Block transfer mode

 One transfer request transfers a block

of the specified size

 Block size is from 1 to 256 bytes or

words

 Up to 65,536 transfers possible

 A block area can be designated at either

the source or destination

• IRQ

• TPU TGI

• 8-bit timer CMI

• SCI TXI or RXI

• A/D converter ADI

• Software

24 bits

7.3.2

Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a

CPU interrupt source when the bit is cleared to 0.

At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. Table 7.3 shows activation source and

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