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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 148 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 148 Page - Renesas Technology Corp |
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148 / 818 page  Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 106 of 772 REJ09B0355-0300 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 0 RAME 1 R/W 2 — 0 — 1 — 0 — Bit Initial value R/W : : : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 Bit 4 INTM1 INTM0 Interrupt Control Mode Description 0 0 0 Interrupts are controlled by I bit (Initial value) 1 1 Interrupts are controlled by I and UI bits and ICR 1 0 — Setting prohibited 1 — Setting prohibited Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG Description 0 Interrupt request generated at falling edge of NMI input (Initial value) 1 Interrupt request generated at rising edge of NMI input |
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