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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H8S2245 датащи(PDF) 669 Page - Renesas Technology Corp |
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H8S2245 датащи(HTML) 669 Page - Renesas Technology Corp |
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669 / 818 page  Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 627 of 772 REJ09B0355-0300 A.3 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8S/2000 CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required for each cycle, depending on its size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × S I + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.4: I = L = 2, J = K = M = N = 0 From table A.3: S I = 4, S L = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.4: I = J = K = 2, L = M = N = 0 From table A.3: S I = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 |
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