H8S2245 datasheet(432/818 Pages) RENESAS

432 / 818 page

Section 11 Watchdog Timer

Rev.3.00 Mar. 26, 2007 Page 390 of 772

REJ09B0355-0300

11.2

11.2.1

Timer Counter (TCNT)

R/W

Bit

Initial value

R/W

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), either the watchdog timer overflow signal (

WDTOVF) or an interval timer interrupt

(WOVI) is generated, depending on the mode selected by the WT/

IT bit in TCSR.

TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared

to 0. It is not initialized in software standby mode.

Note: *

TCNT is write-protected by a password to prevent accidental overwriting. For details

see section 11.2.4, Notes on Register Access.

11.2.2

Timer Control/Status Register (TCSR)

OVF

R/(W)*

WT/

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

R/W

Note: * Can only be written with 0 for flag clearing.

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software

standby mode.

Note: *

TCSR is write-protected by a password to prevent accidental overwriting. For details

see section 11.2.4, Notes on Register Access.

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