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HD6417618 датащи(PDF) 309 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 309 Page - Renesas Technology Corp |
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309 / 646 page ![]() Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 6.00 Jun. 12, 2007 Page 277 of 610 REJ09B0131-0600 12.2.11 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the capacity of the transmit and receive FIFOs. Bit Bit Name Initial value R/W Description 31 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 TFD2 to TFD0 B’000 R Transmit FIFO Capacity Specify the capacity of transmit FIFO. The set value should not be changed after the transmit/receive operation is started. 000: 256 bytes 001: 512 bytes (Setting prohibited in SH7618, setting enabled in SH7618A) Other than above: Setting prohibited 7 to 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 RFD2 to RFD0 B’000 R Receive FIFO Capacity Specify the capacity of receive FIFO. The set value should not be changed after the transmit/receive operation is started. 000: 256 bytes 001: 512 bytes (Setting prohibited in SH7618, setting enabled in SH7618A) Other than above: Setting prohibited |
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