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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 144 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 144 Page - Renesas Technology Corp |
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144 / 646 page  Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 112 of 610 REJ09B0131-0600 7.3.4 Area 0 Memory Type and Memory Bus Width The memory bus width in this LSI can be set for each area. In area 0, the bus width is selected from 8 bits and 16 bits at a power-on reset by the external pin setting. The bus width of other areas is set by the register. The correspondence between the memory type, external pin (MD3), and bus width is listed in table 7.4. Table 7.4 Correspondence between External Pin (MD3), Memory Type, and Bus Width for CS0 MD3 Memory Type Bus Width 1 Normal memory 8 bits 0 16 bits 7.3.5 Data Alignment This LSI supports the big endian and little endian methods of data alignment. The data alignment is specified using the external pin (MD5) at a power-on reset as shown in table 7.5. Table 7.5 Correspondence between External Pin (MD5) and Endians MD5 Endian 0 Big endian 1 Little endian |
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