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HD6417618 датащи(PDF) 115 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 115 Page - Renesas Technology Corp |
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115 / 646 page ![]() Section 6 Interrupt Controller (INTC) Rev. 6.00 Jun. 12, 2007 Page 83 of 610 REJ09B0131-0600 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbr. I/O Function Non-maskable interrupt input pin NMI Input Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ7 Input Input of maskable interrupt request signals 6.3 Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. • Interrupt control register 0 (ICR0) • IRQ control register (IRQCR) • IRQ status register (IRQSR) • Interrupt priority register A (IPRA) • Interrupt priority register B (IPRB) • Interrupt priority register C (IPRC) • Interrupt priority register D (IPRD) • Interrupt priority register E (IPRE) |
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