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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 508 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 508 Page - Renesas Technology Corp |
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508 / 646 page  Section 18 User Break Controller (UBC) Rev. 6.00 Jun. 12, 2007 Page 476 of 610 REJ09B0131-0600 18.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit Bit Name Initial Value R/W Description 31 to 0 BAMB31 to BAMB 0 All 0 R/W Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 18.2.6 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. BDBR selects data used for a break condition in channel B. Bit Bit Name Initial Value R/W Description 31 to 0 BDB31 to BDB 0 All 0 R/W Break Data Bit B Stores data which specifies a break condition in channel B. BDRB specifies the break data on LDB or IDB. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. |
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