HD6417618 datasheet(398/646 Pages) RENESAS

номер детали	HD6417618

подробное описание детали	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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производитель	RENESAS [Renesas Technology Corp]

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 366 of 610

REJ09B0131-0600

Transmitting and Receiving Data: SCIF Initialization (Asynchronous Mode):

Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register

(SCSCR), then initialize the SCIF as follows.

When changing the operation mode or the communication format, always clear the TE and RE bits

to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift

(SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which

retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the

TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the

transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1

and reset SCFTDR before TE is set again to start transmission.

When an external clock is used, the clock should not be stopped during initialization or subsequent

operation. SCIF operation becomes unreliable if the clock is stopped.

HD6417618 датащи(PDF) 398 Page - Renesas Technology Corp