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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618 датащи(PDF) 393 Page - Renesas Technology Corp |
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HD6417618 датащи(HTML) 393 Page - Renesas Technology Corp |
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393 / 646 page  Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 6.00 Jun. 12, 2007 Page 361 of 610 REJ09B0131-0600 14.3.12 Line Status Register (SCLSR) SCLSR is a 16-bit readable/writable register which can always be read from and written to by the CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset. Bit Bit Name Initial value R/W Description 15 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally * 1 [Clearing conditions] • ORER is cleared to 0 when the chip is a power-on reset • ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred * 2 [Setting condition] • ORER is set to 1 when the next serial receiving is finished while receive FIFO data are full. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) hold the data before an overrun error is occurred, and the next receive data is extinguished. When ORER is set to 1, SCIF can not continue the next serial receiving. Note: * The only value that can be written is 0 to clear the flag. |
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