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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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R8C2K датащи(PDF) 241 Page - Renesas Technology Corp |
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R8C2K датащи(HTML) 241 Page - Renesas Technology Corp |
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241 / 471 page  R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 224 of 450 REJ09B0406-0110 16.4.3 Synchronous Operation The TRD1 register is synchronized with the TRD0 register. • Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register. • Synchronous clear When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set to 0000h. Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h. Figure 16.67 Synchronous Operation Value in TRD0 register TRDIOA0 input n n is set n writing Value in TRD1 register n Set to 0000h with TRD0 register Set to 0000h by input capture The above applies under the following conditions: • The SYNC bit in the TRDMR register is set to 1 (synchronous operation). • Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture). Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with the TRD0 register). • Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b. • Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input) The PWM 3 bit in the TRDFCR register is set to 1. n is set |
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