R8C2K datasheet(238/471 Pages) RENESAS

238 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 221 of 450

REJ09B0406-0110

16.4.1

Count Sources

The count source selection method is the same in all modes. However, in PWM3 mode, the external clock

cannot be selected.

i = 0 or 1

NOTE:

1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.

Figure 16.64

Block Diagram of Count Source

Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation

clock of timer RD (refer to Table 16.25 Timer RD Operation Clocks).

When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed on-

chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).

Table 16.35

Count Source Selection

Count Source

Selection

f1, f2, f4, f8, f32

The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.

fOCO40M(1)

The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator

frequency).

Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).

External signal input

to TRDCLK pin

The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

Bits TCK2 to TCK0 in the TRDCRi register are set to 101b

(count source: external clock).

The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.

The PD2_0 bit in the PD2 register is set to 0 (input mode).

TRDCLK/

TRDIOA0

TCK2 to TCK0

TRDi register

TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register

STCLK: Bit in TRDFCR register

f32

= 001b

= 010b

= 011b

= 000b

= 101b

= 100b

Valid edge

selected

CKEG1 to CKEG0

TRDIOA0 I/O or programmable I/O port

Count source

STCLK = 1

STCLK = 0

fOCO40M

= 110b

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