R8C2K datasheet(245/471 Pages) RENESAS

245 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 228 of 450

REJ09B0406-0110

i = 0 or 1, j = either A, B, C, or D

Table 16.37

Input Capture Function Specifications

Item

Specification

Count sources

f1, f2, f4, f8, f32, fOCO40M

External signal input to the TRDCLK pin (valid edge selected by a

program)

Count operations

Increment

Count period

When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b

(free-running operation).

1/fk × 65536 fk: Frequency of count source

Count start condition

1 (count starts) is written to the TSTARTi bit in the TRDSTR register.

Count stop condition

0 (count stops) is written to the TSTARTi bit in the TRDSTR register

when the CSELi bit in the TRDSTR register is set to 1.

Interrupt request generation

timing

• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)

• TRDi register overflows

TRDIOA0 pin function

Programmable I/O port, input-capture input, or TRDCLK (external clock)

input

TRDIOB0, TRDIOC0,

TRDIOD0, TRDIOA1 to

TRDIOD1 pin functions

Programmable I/O port, or input-capture input (selectable by pin)

INT0 pin function

Programmable I/O port or INT0 interrupt input

Read from timer

The count value can be read by reading the TRDi register.

Write to timer

• When the SYNC bit in the TRDMR register is set to 0 (channels 0 and

1 operate independently).

Data can be written to the TRDi register.

• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and

1 operate synchronously).

Data can be written to both the TRD0 and TRD1 registers by writing to

the TRDi register.

Select functions

• Input-capture input pin selected

Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or

TRDIODi.

• Input-capture input valid edge selected

The rising edge, falling edge, or both the rising and falling edges

• The timing when the TRDi register is set to 0000h

At overflow or input capture

• Buffer operation (Refer to 16.4.2 Buffer Operation.)

• Synchronous operation (Refer to 16.4.3 Synchronous Operation.)

• Digital filter

The TRDIOji input is sampled, and when the sampled input level

match as 3 times, the level is determined.

• Input-capture trigger selected

fOCO128 can be selected for input-capture trigger input of the

TRDGRA0 register.

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