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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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R8C2K датащи(PDF) 223 Page - Renesas Technology Corp |
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R8C2K датащи(HTML) 223 Page - Renesas Technology Corp |
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223 / 471 page  R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 206 of 450 REJ09B0406-0110 Figure 16.55 Operating Example of PWM Mode m n p TRC register value Count source m+1 n+1 TRCIOC output q m-n p+1 m-p m-q q+1 TRCIOD output m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value q: TRCGRD register setting value Inactive level is “L” Active level is “H” Active level is “L” “L” initial output until compare match “H” initial output until compare match Set to 0 by a program Set to 0 by a program Set to 0 by a program TRCIOB output IMFA bit in TRCSR register 1 0 IMFB bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 IMFD bit in TRCSR register 1 0 The above applies under the following conditions: • Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers). • Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled). • In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”). Set to 0 by a program |
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