R8C2K datasheet(222/471 Pages) RENESAS

222 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 205 of 450

REJ09B0406-0110

Figure 16.54

TRCCR1 Register in PWM Mode

j = A, B, C, or D

BFC, BFD: Bits in TRCMR register

NOTE:

1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM

period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.

Table 16.21

Functions of TRCGRj Register in PWM Mode

Setting

PWM Output Pin

TRCGRA

−

General register. Set the PWM period.

−

TRCGRB

−

General register. Set the PWM output change point.

TRCIOB

TRCGRC

BFC = 0

General register. Set the PWM output change point.

TRCIOC

TRCGRD

BFD = 0

TRCIOD

TRCGRC

BFC = 1

Buffer register. Set the next PWM period. (Refer to 16.3.3.2

Buffer Operation

−

TRCGRD

BFD = 1

Buffer register. Set the next PWM output change point. (Refer to

16.3.3.2 Buffer Operation

TRCIOB

Timer RC Control Register 1

Symbol

Address

After Reset

TRCCR1

0121h

00h

Bit Symbol

Bit Name

Function

j = B, C or D

NOTES:

2. If the pin function is set for w aveform output (refer to Tables 7.12 to 7.13 and Tables 7.29 to 7.32), the initial output

level is output w hen the TRCCR1 register is set.

b3 b2

TOD

b1 b0

b7 b6 b5 b4

TRCIOC output level select bit(1, 2)

Disabled in PWM mode

TOA

TOB

TRCIOA output level select bit(1)

TRCIOB output level select bit(1, 2)

Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).

TOC

TRCIOD output level select bit(1, 2)

CCLR

0 : Active level “H”

(Initial output “L”

“H” output by compare match in

the TRCGRj register

“L” output by compare match in

the TRCGRA register

1 : Active level “L”

(Initial output “H”

“L” output by compare match in

the TRCGRj register

“H” output by compare match in

the TRCGRA register

TRC counter clear select bit

TCK2

Count source select bits(1)

b6 b5 b4

0 0 0 : f1

0 0 1 : f2

0 1 0 : f4

0 1 1 : f8

1 0 0 : f32

1 0 1 : TRCCLK input rising edge

1 1 0 : fOCO40M

1 1 1 : Do not set.

0 : Disable clear (free-running operation)

1 : Clear by compare match in the

TRCGRA register

TCK0

TCK1

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